Existing low dropout (LDO) regulator architecture uses analog voltage to control the gate drive to the LDO. Generating the analog voltage may require careful design of the circuit generating the analog circuit. Generally such circuits do not scale well with process technologies. To regulate the output voltage of the LDO, head room (e.g., of about 50 mV to 100 mV) may be required between the input power supply voltage and the output voltage of the LDO. With respect to the analog LDO approach, there are many challenges.
For example, stability of the feedback loop of the analog LDO may be extremely dependent on package parasitic and the output pole. As a result, to gain stability of the feedback loop a penalty in bandwidth may be made. The analog LDO may also exhibit a minimum dropout at its output node (e.g., 50 mV to 100 mV) for LDO normal operation. When input power supplies are getting lower, such minimum dropout becomes a challenge. The analog LDO may also exhibit a finite direct-current (DC) offset error due to gain limitations that affect the DC set point accuracy. There are also multiple integration and design challenges in analog designs, especially those that use dual loop architecture.